Semiconductor device including a gate electrode and a conductive structure

ABSTRACT

A semiconductor device including: a conductor disposed on a substrate; a first contact disposed on the conductor; a second contact having a first portion disposed on the first contact and a second portion protruded away from the first portion in a direction parallel to the substrate, wherein the first and second contacts are disposed in an insulating layer; a via disposed on the insulating layer and the second portion of the second contact; and a metal line disposed on the via.

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. non-provisional patent application claims priority under 35U.S.C. § 119 to Korean Patent Application Nos. 10-2015-0162668,10-2015-0162675, 10-2016-0048379 and 10-2016-0086996, filed on Nov. 19,2015, Nov. 19, 2015, Apr. 20, 2016 and Jul. 8, 2016, respectively, inthe Korean Intellectual Property Office, the disclosures of which areincorporated by reference herein in their entireties.

TECHNICAL FIELD

The present inventive concept relates to semiconductor devices andmethods of fabricating the same, and more particularly, to semiconductordevices including field effect transistors and methods of fabricatingthe same.

Discussion of Related Art

Due to their small-sizes, multifunctional, and/or low-costcharacteristics, semiconductor devices are ubiquitous in the electronicindustry. Semiconductor devices may be a memory device for storing data,a logic device for processing data, or a hybrid device including both ofmemory and logic elements. To meet increased demand for electronicdevices with fast speed and/or low power consumption, semiconductordevices with high reliability, high performance, and/or multiplefunctions are desired. To satisfy these technical requirements, thecomplexity and/or integration density of semiconductor devices are beingincreased.

SUMMARY

According to an exemplary embodiment of the present inventive concept,there is provided a semiconductor device including: a conductor disposedon a substrate; a first contact disposed on the conductor; a secondcontact having a first portion disposed on the first contact and asecond portion protruded away from the first portion in a directionparallel to the substrate, wherein the first and second contacts aredisposed in an insulating layer; a via disposed on the insulating layerand the second portion of the second contact; and a metal line disposedon the via.

According to an exemplary embodiment of the present inventive concept,there is provided a semiconductor device including: a dummy conductordisposed on a substrate; a first contact disposed on the dummyconductor; a trench silicide disposed on the substrate and spaced apartfrom the dummy conductor; a second contact disposed on the trenchsilicide; and a third contact directly disposed on the first and secondcontacts and connecting the first and second contacts to each other.

According to an exemplary embodiment of the present inventive concept,there is provided a semiconductor device including: a first conductordisposed on a substrate; a first contact disposed on the firstconductor; a second contact disposed on the substrate and spaced apartfrom the first conductor and the first contact; and a third contactdirectly disposed on the first and second contacts and connecting thefirst and second contacts to each other.

According to an exemplary embodiment of the present inventive concept,there is provided a semiconductor device including: a first trenchsilicide disposed on a substrate; a first contact disposed on an uppersurface of the first trench silicide, wherein the upper surface of thefirst trench silicide is wider than a lower surface of the firstcontact; a second trench silicide disposed on the substrate; a secondcontact disposed on the second trench silicide; and a third contactdirectly disposed on the first and second contacts and connecting thefirst and second contacts to each other.

According to an exemplary embodiment of the present inventive concept,there is provided a semiconductor device including: a first contactdisposed on a substrate and extending lengthwise in a first direction; asecond contact disposed on the substrate and extending lengthwise in thefirst direction; a conductor disposed between the first and secondcontacts and extending lengthwise in the first direction; and a thirdcontact disposed on the first and second contacts and extendinglengthwise in a second direction crossing the first direction, wherein afirst portion of the third contact protrudes beyond an edge of the firstcontact such that the first contact is disposed between the firstportion and the conductor in the second direction.

According to an exemplary embodiment of the present inventive concept,there is provided a semiconductor device including: a first conductordisposed on a substrate; a first contact disposed on the firstconductor; a second conductor disposed on the substrate and spaced apartfrom the first conductor; a second contact disposed on the secondconductor; and a third contact directly disposed on the first and secondcontacts and connecting the first and second contacts to each other.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a computer system for performinga semiconductor design process, according to exemplary embodiments ofthe present inventive concept.

FIG. 2 is a flow chart illustrating a method of designing andfabricating a semiconductor device, according to exemplary embodimentsof the present inventive concept.

FIG. 3 is a layout diagram illustrating a portion of a standard celllayout according to exemplary embodiments of the present inventiveconcept.

FIG. 4 is a perspective view illustrating a semiconductor device that isformed based on the layout of FIG. 3 according to exemplary embodimentsof the preset inventive concept.

FIG. 5 is a layout diagram illustrating a portion of a standard celllayout according to exemplary embodiments of the present inventiveconcept.

FIG. 6 is a perspective view illustrating a semiconductor device that isformed based on the layout of FIG. 5 according to exemplary embodimentsof the preset inventive concept.

FIG. 7 is a layout diagram illustrating a portion of a standard celllayout according to exemplary embodiments of the present inventiveconcept.

FIG. 8 is a perspective view illustrating a semiconductor device that isformed based on the layout of FIG. 7 according to exemplary embodimentsof the preset inventive concept.

FIG. 9 is a layout diagram illustrating a portion of a standard celllayout according to exemplary embodiments of the present inventiveconcept.

FIG. 10 is a perspective view illustrating a semiconductor device thatis formed based on the layout of FIG. 9 according to exemplaryembodiments of the preset inventive concept.

FIG. 11 is a layout diagram illustrating a portion of a standard celllayout according to exemplary embodiments of the present inventiveconcept.

FIG. 12 is a perspective view illustrating a semiconductor deviceaccording to exemplary embodiments of the present inventive concept.

FIG. 13 is a layout diagram including standard cell layouts according toexemplary embodiments of the present inventive concept.

FIG. 14A is a layout diagram illustrating a region ‘M’ of FIG. 13according to exemplary embodiments of the present inventive concept.

FIG. 14B is a layout diagram illustrating the region ‘M’ of FIG. 13according to a comparative example.

FIG. 15A is a layout diagram illustrating a region ‘N’ of FIG. 13according to exemplary embodiments of the inventive concept.

FIG. 15B is a layout diagram illustrating the region ‘N’ of FIG. 13according to a comparative example.

FIG. 16 is a plan view illustrating a semiconductor device according toexemplary embodiments of the inventive concept.

FIGS. 17A, 17B, 17C, 17D, 17E, 17F, 17G, 17H, 17I, 17J, 17K, 17L, 17M,17N, 17O, 17P, 17Q and 17R are sectional views taken along lines A-A′,B-B′, C-C′, D-D′, E-E′, F-F′, G-G′, H-H′, I-I′, J-J′, K-K′, L-L′, M-M′,N-N′, O-O′, P-P′, Q-Q′, and R-R′, respectively, of FIG. 16 according toexemplary embodiments of the preset inventive concept.

FIGS. 18A and 18B are sectional views taken along the line A-A′ of FIG.16 to illustrate a semiconductor device according to exemplaryembodiments of the present inventive concept.

FIG. 18C is a sectional view taken along the line F-F′ of FIG. 16 toillustrate a semiconductor device according to exemplary embodiments ofthe present inventive concept.

FIGS. 19, 21, 23, 25, 27, 29, and 31 are plan views illustrating amethod of fabricating a semiconductor device, according to exemplaryembodiments of the present inventive concept.

FIGS. 20A, 22A, 24A, 26A, 28A, 30A, and 32A are sectional views takenalong lines A-A′ of FIGS. 19, 21, 23, 25, 27, 29, and 31, respectively,according to exemplary embodiments of the preset inventive concept.

FIGS. 20B, 22B, 24B, 26B, 28B, 30B, and 32B are sectional views takenalong lines B-B′ of FIGS. 19, 21, 23, 25, 27, 29, and 31, respectively,according to exemplary embodiments of the preset inventive concept.

FIGS. 22C, 24C, 26C, 28C, 30C, and 32C are sectional views taken alonglines C-C′ of FIGS. 21, 23, 25, 27, 29, and 31, respectively, accordingto exemplary embodiments of the preset inventive concept.

FIGS. 28D, 30D, and 32D are sectional views taken along lines D-D′ ofFIGS. 27, 29, and 31, respectively, according to exemplary embodimentsof the preset inventive concept.

FIGS. 30E and 32E are sectional views taken along lines E-E′ of FIGS. 29and 31, respectively, according to exemplary embodiments of the presetinventive concept.

FIG. 33 is a plan view illustrating a semiconductor device that isfabricated based on standard cell layouts according to an exemplaryembodiment of the present inventive concept.

FIG. 34 is a plan view illustrating a semiconductor device according toexemplary embodiments of the present inventive concept.

FIGS. 35A through 35C are sectional views taken along lines A-A′, B-B′,and C-C′ of FIG. 34, respectively, according to exemplary embodiments ofthe preset inventive concept.

DETAILED DESCRIPTION OF THE EMBODIMENTS

FIG. 1 is a block diagram illustrating a computer system for performinga semiconductor design process, according to exemplary embodiments ofthe present inventive concept. Referring to FIG. 1, a computer systemmay include a central processing unit (CPU) 10, a working memory 30, aninput-output device 50, and an auxiliary memory device 70. In exemplaryembodiments of the present inventive concept, the computer system may bea customized system for performing a layout design process according toexemplary embodiments of the present inventive concept. Furthermore, thecomputer system may include a computing system configured to executevarious design and check simulation programs.

The CPU 10 may be configured to run a variety of software, such asapplication programs, operating systems, and device drivers. Forexample, the CPU 10 may be configured to run an operating system loadedon the working memory 30. Furthermore, the CPU 10 may be configured torun various application programs on the operating system. For example,the CPU 10 may be configured to run a layout design tool 32 loaded onthe working memory 30.

The operating system or application programs may be loaded on theworking memory 30. For example, when the computer system starts abooting operation, an operating system (OS) image stored in theauxiliary memory device 70 may be loaded on the working memory 30according to a booting sequence. In the computer system, input/outputoperations may be managed by the operating system. Certain applicationprograms, which may be selected by a user or be provided for basicservices, may be loaded on the working memory 30. According to exemplaryembodiments of the present inventive concept, the layout design tool 32prepared for a layout design process may be loaded on the working memory30, from the auxiliary memory device 70.

The layout design tool 32 may provide a function for changing biasingdata for specific layout patterns. For example, the layout design tool32 may be configured to allow the specific layout patterns to haveshapes and positions different from those defined by a design rule. Thelayout design tool 32 may be configured to perform a design rule check(DRC) under the changed condition of the biasing data. The workingmemory 30 may be a volatile memory device (e.g., a static random accessmemory (SRAM) or dynamic random access memory (DRAM) device) or anonvolatile memory device (e.g., a phase change random access memory(PRAM), magnetoresistive random access memory (MRAM), resistive randomaccess memory (ReRAM), ferroelectric (FRAM), or NOR FLASH memorydevice).

In addition, a simulation tool 34 may be loaded on the working memory 30to perform an optical proximity correction (OPC) operation on thedesigned layout data.

The input-output device 50 may be configured to control user input andoutput operations of user interface devices. For example, theinput-output device 50 may include a keyboard or a monitor, allowing adesigner to input relevant information. By using the input-output device50, the designer may receive information on several regions or datapaths, to which adjusted operating characteristics can be applied, of asemiconductor device. The input-output device 50 may be configured todisplay a progress status or a process result of the simulation tool 34.

The auxiliary memory device 70 may be a storage medium for the computersystem. The auxiliary memory device 70 may be configured to storeapplication programs, an OS image, and various data. The auxiliarymemory device 70 may be provided in the form of memory cards (e.g., amultimedia card (MMC), an embedded multimedia card (eMMC), securedigital (SD), MicroSD, and so forth) or a hard disk drive (HDD). Theauxiliary memory device 70 may include a NAND FLASH memory device with alarge memory capacity. The auxiliary memory device 70 may includenonvolatile memory devices (e.g., PRAM, MRAM, ReRAM, or FRAM) or NORFLASH memory devices.

A system interconnector 90 may serve as a system bus for realizing anetwork in the computer system. The CPU 10, the working memory 30, theinput-output device 50, and the auxiliary memory device 70 may beelectrically connected to each other through the system interconnector90, and thus, data may be exchanged therebetween. However, the systeminterconnector 90 may not be limited to the afore-describedconfiguration. For example, the system interconnector 90 may include anadditional element for increasing efficiency in data communication.

FIG. 2 is a flow chart illustrating a method of designing andfabricating a semiconductor device, according to exemplary embodimentsof the present inventive concept.

Referring to FIG. 2, a high-level design process for a semiconductorintegrated circuit may be performed using the computer system describedwith reference to FIG. 1 (in S110). For example, in the high-leveldesign process, an integrated circuit to be designed may be described interms of a high-level computer language (e.g., C language). Circuitsdesigned by the high-level design process may be more concretelydescribed by a register transfer level (RTL) coding or a simulation.Furthermore, codes generated by the RTL coding may be converted into anetlist, and the results may be combined with each other to whollydescribe a semiconductor device. The combined schematic circuit may beverified by a simulation tool. In exemplary embodiments of the presentinventive concept, an adjusting step may be further performed, inconsideration of a result of the verification step.

A layout design process may be performed to realize a logically completeform of the semiconductor integrated circuit on a silicon wafer (inS120). For example, the layout design process may be performed, based onthe schematic circuit prepared in the high-level design process or thecorresponding netlist. The layout design process may include a routingstep of placing and connecting various standard cells that are providedfrom a cell library, based on a predetermined design rule. A diffusionprevention pattern may be introduced at a boundary of at least one ofthe standard cells and may be configured to have technical featuressuitable for electric characteristics of the corresponding standardcell. Such a redesigned standard cell may be provided in the celllibrary.

The cell library may contain information on operation, speed, and powerconsumption of a plurality of cells. In exemplary embodiments of thepresent inventive concept, a cell library for representing a layout of acircuit in a gate level may be defined in or by the layout design tool.Here, the layout may be prepared to define or describe shapes,positions, or dimensions of patterns constituting transistors and metalinterconnection lines, which will be actually formed on a silicon wafer.For example, to actually form an inverter circuit on a silicon wafer, itmay be necessary to prepare or draw a layout for patterns (e.g.,p-channel metal oxide semiconductor (PMOS), n-channel metal oxidesemiconductor (NMOS), N-WELL, gate electrodes, and metal interconnectionlines thereon). For this reason, at least one of the inverters definedin the cell library may be selected.

A routing step of connecting the selected cells to each other may alsobe performed. For example, the routing step may be performed on theselected and disposed standard cells to connect them to upperinterconnection lines. These steps may be automatically or manuallyperformed in the layout design tool. In exemplary embodiments of thepresent inventive concept, a step of placing the standard cells andestablishing routing structures thereto may be automatically performedby a Place & Routing tool.

After the routing step, a verification step may be performed on thelayout to check whether there is a portion violating the design rule. Inexemplary embodiments of the present inventive concept, the verificationstep may include evaluating verification items, such as a design rulecheck (DRC), an electrical rule check (ERC), and a layout vs. schematic(LVS). The evaluating of the DRC item may be performed to evaluatewhether the layout meets the design rule. The evaluating of the ERC itemmay be performed to evaluate whether there is an issue of electricaldisconnection in the layout. The evaluating of the LVS item may beperformed to evaluate whether the layout is prepared to coincide withthe gate-level netlist.

An optical proximity correction (OPC) step may be performed (in S130).The OPC step may be performed to correct optical proximity effects,which may occur when a photolithography process is performed on asilicon wafer using a photomask manufactured based on the layout. Theoptical proximity effect may be an unintended optical effect (such asrefraction or diffraction) which may occur in the exposing process usingthe photomask manufactured based on the layout. In the OPC step, thelayout may be modified to have a reduced difference in shape betweendesigned patterns and actually-formed patterns, which may be caused bythe optical proximity effects. As a result of the optical proximitycorrection step, the designed shapes and positions of the layoutpatterns may be slightly changed.

A photomask may be manufactured, based on the layout modified by the OPCstep (in S140). For example, the photomask may be manufactured bypatterning a chromium layer provided on a glass substrate, using thelayout pattern data.

The photomask manufactured may be used to manufacture a semiconductordevice (in S150). In the actual fabricating process, the exposing andetching steps may be repeatedly performed, and thus, patterns defined inthe layout design process may be sequentially formed on a semiconductorsubstrate.

FIG. 3 is a layout diagram illustrating a portion of a standard celllayout according to exemplary embodiments of the present inventiveconcept.

Referring to FIG. 3, a standard cell layout may include a layout for anactive region AR (hereinafter, also referred to as an active region AR),a layout for a gate electrode GE (hereinafter, also referred to as agate pattern GP), a layout for a conductive structure CP (hereinafter,also referred to as a conductive pattern CL), a layout for a via(hereinafter, also referred to as via pattern V0), and a layout for aninterconnection line ML (hereinafter, also referred to as a conductiveline M1).

The active region AR may be a PMOSFET region or an NMOSFET region. Thegate pattern GP may cross the active region AR and extend in a firstdirection D1. A portion of the active region AR, which is not overlappedwith the gate pattern GP, may serve as a source/drain region SD.

The conductive pattern CL may include a connection pattern M0 and anactive contact pattern CA. The active contact pattern CA may be disposedon the active region AR. The active contact pattern CA may be spacedapart from the gate pattern GP in a second direction D2 crossing thefirst direction D1. The connection pattern M0 and the active contactpattern CA may be partially overlapped with each other. The connectionpattern M0 may extend in the second direction D2.

The via pattern V0 and the conductive line M1 may be disposed on theconnection pattern M0. The via pattern V0 may be overlapped with theconnection pattern M0 but may be spaced apart from the active contactpattern CA in the second direction D2. The conductive line M1 may beoverlapped with the via pattern V0 and may extend in the first directionD1.

FIG. 4 is a perspective view illustrating a semiconductor deviceaccording to exemplary embodiments of the present inventive concept. Forexample, FIG. 4 is a perspective view illustrating a semiconductordevice that is formed based on the layout of FIG. 3.

Referring to FIG. 4, a substrate 100 with an active pattern FN may beprovided. The active pattern FN may be formed in accordance with theactive region AR described with reference to FIG. 3. The active patternFN may include a pair of source/drain regions SD and a channel region AFbetween the source/drain regions SD.

A gate electrode GE may be disposed on the channel region AF to crossthe active pattern FN. The gate electrode GE may extend in a firstdirection D1 parallel to a top surface of the substrate 100. The gateelectrode GE may be a pattern that is formed in accordance with the gatepattern GP described with reference to FIG. 3. A gate insulating patternmay be interposed between the channel region AF and the gate electrodeGE. The gate electrode GE may include doped semiconductor materials,conductive metal nitrides (e.g., titanium nitride or tantalum nitride),or metals (e.g., aluminum or tungsten).

A conductive structure CP may be provided on at least one of thesource/drain regions SD. The conductive structure CP may include a firstportion P1 and a second portion P2. The conductive structure CP may be apattern that is formed in accordance with the conductive pattern CLpreviously described with reference to FIG. 3. For example, the firstportion P1 may be a pattern that is formed in accordance with theconnection pattern M0 described with reference to FIG. 3, and the secondportion P2 may be a pattern that is formed in accordance with the activecontact pattern CA previously described with reference to FIG. 3.

The second portion P2 may be electrically connected to the source/drainregion SD. For example, the second portion P2 may serve as a contactplug that is in direct contact with the source/drain region SD. Thesecond portion P2 may be spaced apart from the gate electrode GE in asecond direction D2 crossing the first direction D1. The second portionP2 may extend in the first direction D1.

The first portion P1 may extend from the second portion P2 in the seconddirection D2. Furthermore, the first portion P1 may include a first endportion TP1 protruding from at least one sidewall (e.g., a firstsidewall SW1) of the second portion P2. The first sidewall SW1 may be asidewall that extends in the first direction D1 and faces the gateelectrode GE. In other words, the first portion P1 may have a shapepassing through a top portion of the second portion P2.

A top surface P1 t of the first portion P1 may be substantially coplanarwith a top surface P2 t of the second portion P2. A bottom surface P1 bof the first portion P1 may be positioned at a level higher than that ofa bottom surface P2 b of the second portion P2. In other words, thebottom surface P1 b of the first portion is higher than the bottomsurface P2 b of the second portion P2 with respect to an upper surfaceof the substrate 100. In addition, the bottom surface P1 b of the firstportion P1 may be positioned at a level higher than that of the topsurface of the gate electrode GE.

The first portion P1 and the second portion P2 may be connected to eachother to constitute the conductive structure CP, which is provided inthe form of a single body. The conductive structure CP may includeconductive metal nitrides (e.g., titanium nitride or tantalum nitride)or metals (e.g., aluminum or tungsten).

An interconnection line ML may be provided on the conductive structureCP. The interconnection line ML may include a line portion LI extendingin the first direction D1 and a contact portion VI vertically connectingthe line portion LI to the conductive structure CP. The line portion LImay be a pattern that is formed in accordance with the conductive lineM1 previously described with reference to FIG. 3, and the contactportion VI may be a pattern that is formed in accordance with the viapattern V0 previously described with reference to FIG. 3. Theinterconnection line ML may include conductive metal nitrides (e.g.,titanium nitride or tantalum nitride) or metals (e.g., aluminum ortungsten).

When viewed in a plan view, the line portion LI may be spaced apart fromthe second portion P2 in the second direction D2. However, the lineportion LI may be electrically connected to the second portion P2through the contact portion VI and the first portion P1. In other words,the line portion LI may be electrically connected to the source/drainregion SD. As a result, when the line portion LI is horizontally spacedapart from the second portion P2, the line portion LI and the secondportion P2 may be electrically connected to each other through the firstportion P1. This may allow electrical signals to be input to or outputfrom the source/drain region SD through the interconnection line ML.

Referring back to FIG. 3, the connection pattern M0 of the conductivepattern CL may be used to increase a degree of freedom in placing theconductive line M1 in a layout design process. As a result, the routingstep described with reference to FIG. 2 can be easily performed on astandard cell layout.

FIG. 5 is a layout diagram illustrating a portion of a standard celllayout according to exemplary embodiments of the present inventiveconcept. In the following description of the present embodiment, anelement previously described with reference to FIG. 3 may not bedescribed in much further detail for the sake of brevity.

Referring to FIG. 5, a standard cell layout may include an active regionAR, a gate pattern GP, a conductive pattern CL, a via pattern V0, and aconductive line M1. The conductive pattern CL may include a connectionpattern M0 and a gate contact pattern CB. The gate contact pattern CBmay be disposed on the gate pattern GP. The gate contact pattern CB maybe overlapped with the connection pattern M0. The connection pattern M0may have a longitudinal axis that is parallel to a second direction D2.

The via pattern V0 and the conductive line M1 may be disposed on theconnection pattern M0. The via pattern V0 may be overlapped with theconnection pattern M0 but may be spaced apart from the gate contactpattern CB in the second direction D2. The conductive line M1 may beoverlapped with the via pattern V0 and may extend in a first directionD1.

FIG. 6 is a perspective view illustrating a semiconductor deviceaccording to exemplary embodiments of the present inventive concept. Forexample, FIG. 6 is a perspective view illustrating a semiconductordevice that is formed based on the layout of FIG. 5. In the followingdescription of the present embodiment, an element previously describedwith reference to FIG. 4 may not be described in much further detail forthe sake of brevity.

Referring to FIG. 6, a conductive structure CP may be disposed on a gateelectrode GE. The conductive structure CP may include a first portion P1and a third portion P3. The third portion P3, not the second portion P2,may be provided in the conductive structure CP, unlike the conductivestructure CP previously described with reference to FIG. 4. The firstportion P1 may be a pattern that is formed in accordance with theconnection pattern M0 previously described with reference to FIG. 5, andthe third portion P3 may be a pattern that is formed in accordance withthe gate contact pattern CB previously described with reference to FIG.5.

The third portion P3 may be electrically connected to the gate electrodeGE. For example, the third portion P3 may serve as a contact plug thatis in direct contact with the source/drain regions SD. The third portionP3 may be vertically spaced apart from the source/drain regions SD.

The first portion P1 may be extended from the third portion P3 in adirection opposite to the second direction D2. Furthermore, the firstportion P1 may include second end portions TP2 protruding from bothsidewalls (e.g., second sidewalls SW2) of the third portion P3. In otherwords, the first portion P1 may have a line width greater than that ofthe third portion P3.

A top surface P1 t of the first portion P1 may be substantially coplanarwith a top surface P3 t of the third portion P3. A bottom surface P1 bof the first portion P1 may be higher than a bottom surface P3 b of thethird portion P3. For example, the bottom surface P1 b of the firstportion P1 is higher than the bottom surface P3 b of the third portionP3 with respect to an upper surface of the substrate 100. Since thebottom surface P3 b of the third portion P3 is positioned atsubstantially the same level as the top surface of the gate electrodeGE, the bottom surface P1 b of the first portion P1 may be higher thanthe top surface of the gate electrode GE.

An interconnection line ML may be provided on the conductive structureCP. When viewed in a plan view, a line portion LI of the interconnectionline ML may be spaced apart from the third portion P3 in the seconddirection D2. However, the line portion LI may be electrically connectedto the third portion P3 via a contact portion VI and the first portionP1. For example, the line portion LI may be electrically connected tothe gate electrode GE. As a result, when the line portion LI ishorizontally spaced apart from the third portion P3, the line portion LIand the third portion P3 may be electrically connected to each otherthrough the first portion P1. This may allow electrical signals to beinput or output to or from the gate electrode GE through theinterconnection line ML.

FIG. 7 is a layout diagram illustrating a portion of a standard celllayout according to exemplary embodiments of the present inventiveconcept. In the following description of the present embodiment, anelement previously described with reference to FIGS. 3 and 5 may not bedescribed in much further detail for the sake of brevity.

Referring to FIG. 7, a standard cell layout may include an active regionAR, a gate pattern GP, a conductive pattern CL, a via pattern V0, and aconductive line M1. The conductive pattern CL may include a connectionpattern M0, an active contact pattern CA and a gate contact pattern CB.

The active contact pattern CA may be disposed on the active region AR,and the gate contact pattern CB may be disposed on the gate pattern GP.The active contact pattern CA and the connection pattern M0 may bepartially overlapped with each other, and the gate contact pattern CBmay be overlapped with the connection pattern M0.

To reduce complexity in the drawings and to provide better understandingof exemplary embodiments of the inventive concept, the via pattern V0and the conductive line M1 are not shown in FIG. 7; however, they may befreely disposed on the connection pattern M0, as previously describedwith reference to FIGS. 3 and 5, for example.

FIG. 8 is a perspective view illustrating a semiconductor deviceaccording to exemplar embodiments of the present inventive concept. Forexample, FIG. 8 is a perspective view illustrating a semiconductordevice that is formed based on the layout of FIG. 7. In the followingdescription of the present embodiment, an element previously describedwith reference to FIGS. 4 and 6 may not be described in much furtherdetail for the sake of brevity.

Referring to FIG. 8, a conductive structure CP may be disposed on asubstrate 100. The conductive structure CP may include a first portionP1, a second portion P2, and a third portion P3. The second portion P2may be disposed on and electrically connected to the source/drain regionSD, and the third portion P3 may be disposed on and electricallyconnected to the gate electrode GE. The first portion P1 may extend in asecond direction D2 and may connect the second portion P2 and the thirdportion P3 to each other.

A top surface P1 t of the first portion P1, a top surface P2 t of thesecond portion P2, and a top surface P3 t of the third portion P3 may besubstantially coplanar with each other. A bottom surface P1 b of thefirst portion P1, a bottom surface P2 b of the second portion P2, and abottom surface P3 b of the third portion P3 may be positioned atdifferent heights with respect to an upper surface of the substrate 100.For example, the bottom surface P1 b of the first portion P1 may behigher than the bottom surface P3 b of the third portion P3, and thebottom surface P3 b of the third portion P3 may be higher than thebottom surface P2 b of the second portion P2.

An interconnection line ML, as previously described with reference toFIGS. 3 and 5, may be provided on the conductive structure CP.

FIG. 9 is a layout diagram illustrating a portion of a standard celllayout according to exemplary embodiments of the present inventiveconcept. In the following description of the present embodiment, anelement previously described with reference to FIG. 3 may not bedescribed in much further detail for the sake of brevity.

Referring to FIG. 9, a standard cell layout may include an active regionAR, a gate pattern GP, a conductive pattern CL, a via pattern V0, and aconductive line M1. The conductive pattern CL may include a connectionpattern M0 and a pair of active contact patterns CA.

The active contact patterns CA may be respectively disposed on oppositeportions of the active region AR that are positioned at both sides ofthe gate pattern GP. Each of the active contact patterns CA may beoverlapped with the connection pattern M0. The connection pattern M0 maycross the gate pattern GP and extend in a second direction D2.

To reduce complexity in the drawings and to provide better understandingof exemplary embodiments of the present inventive concept, the viapattern V0 and the conductive line M1 are not shown in FIG. 9; however,they may be freely disposed on the connection pattern M0, as previouslydescribed with reference to FIG. 3, for example.

FIG. 10 is a perspective view illustrating a semiconductor deviceaccording to exemplary embodiments of the present inventive concept. Forexample, FIG. 10 is a perspective view illustrating a semiconductordevice that is formed based on the layout of FIG. 9. In the followingdescription of the present embodiment, an element previously describedwith reference to FIG. 4 may not be described in much further detail forthe sake of brevity.

Referring to FIG. 10, a conductive structure CP may be disposed on asubstrate 100. The conductive structure CP may include a first portionP1 and a pair of second portions P2. The second portions P2 may bedisposed on and electrically connected to the source/drain regions SD,respectively, which are disposed at both sides of the gate electrode GE.Here, the first portion P1 may be formed to cross the gate electrode GEand extend in a second direction D2 and may be used to connect thesecond portions P2 to each other. In other words, the first portion P1may connect the second portions P2, which are spaced apart from eachother with the gate electrode GE interposed therebetween, to each other.

An interconnection line ML may be provided on the conductive structureCP, as previously described with reference to FIG. 3.

FIG. 11 is a layout diagram illustrating a portion of a standard celllayout according to exemplary embodiments of the present inventiveconcept. In the following description of the present embodiment, anelement previously described with reference to FIG. 5 may not bedescribed in much further detail for the sake of brevity.

Referring to FIG. 11, a standard cell layout may include an activeregion AR, gate patterns GP, a conductive pattern CL, a via pattern V0,and a conductive line M1. The conductive pattern CL may include aconnection pattern M0 and a pair of gate contact patterns CB.

The gate contact patterns CB may be disposed on the gate patterns GP,respectively. The gate contact patterns CB may be overlapped with theconnection pattern M0. The connection pattern M0 may cross the gatepatterns GP and extend in a second direction D2.

To reduce complexity in the drawings and to provide better understandingof exemplary embodiments of the present inventive concept, the viapattern V0 and the conductive line M1 are not shown in FIG. 11; however,they may be freely disposed on the connection pattern M0, as previouslydescribed with reference to FIG. 5, for example.

FIG. 12 is a perspective view illustrating a semiconductor deviceaccording to exemplary embodiments of the present inventive concept. Forexample, FIG. 12 is a perspective view illustrating a semiconductordevice that is formed based on the layout of FIG. 11. In the followingdescription of the present embodiment, an element previously describedwith reference to FIG. 6 may not be described in much further detail forthe sake of brevity.

Referring to FIG. 12, a conductive structure CP may be disposed on gateelectrodes GE that are formed on a substrate 100. The conductivestructure CP may include a first portion P1 and a pair of third portionsP3. The third portions P3 may be electrically connected to the gateelectrodes GE, respectively. Here, the first portion P1 may extend in asecond direction D2 to cross the gate electrodes GE, and the thirdportions P3 may be connected to each other by the first portion P1.

An interconnection line ML may be provided on the conductive structureCP, as previously described with reference to FIG. 3.

FIG. 13 is a layout diagram including standard cell layouts according toexemplary embodiments of the present inventive concept. In the followingdescription of the present embodiment, an element previously describedwith reference to FIGS. 3, 5, 7, 9, and 11 may not be described in muchfurther detail for the sake of brevity.

Referring to FIG. 13, a layout design tool may be used to disposestandard cell layouts side by side. As an example, the standard celllayouts may include first to third standard cell layouts STD1, STD2, andSTD3. The first to third standard cell layouts STD1, STD2, and STD3 maybe arranged in a second direction D2. Each of the first to thirdstandard cell layouts STD1, STD2, and STD3 may include a logic layoutfor logic transistors, an interconnection line layout forinterconnection lines provided on the logic transistors, and a contactlayout for contacts connecting the logic transistors and theinterconnection lines to each other.

The logic layout may include active layouts for active regions. Theactive layouts may include a PMOSFET region PR and an NMOSFET region NR.The PMOSFET region PR and the NMOSFET region NR may be spaced apart fromeach other in a first direction D1 crossing the second direction D2.

The logic layout may include layouts (e.g., gate patterns GP) for gateelectrodes, which extend in the first direction D1 and cross the PMOSFETregion PR and the NMOSFET region NR. The gate patterns GP may be spacedapart from each other in the second direction D2. The PMOSFET region PR,the NMOSFET region NR, and the gate patterns GP may constitute logictransistors provided on a semiconductor substrate 100.

The contact layout may include layouts (e.g., lower conductive patternsLP) for a lower conductive structure overlapped with or connected toeach of the PMOSFET region PR and the NMOSFET region NR, layouts (e.g.,connection patterns M0 a-M0 h) for connection patterns M0, layouts(e.g., active contact patterns CAa-CAl) for an active contact ACoverlapped with or connected to the lower conductive patterns LP, andlayouts (e.g., gate contact patterns CBa-CBh) for gate contacts GCoverlapped with or connected to the gate patterns GP. Each of theconnection patterns M0 a-M0 h may be overlapped with or connected to atleast one of the active contact patterns CAa-CAl and the gate contactpatterns CBa-CBh. In addition, layouts (e.g., conductive patternsCL1-CL8) for a conductive structure CP may be defined in the contactlayout. The conductive patterns CL1-CL8 may include first to eighthconductive patterns CL1-CL8.

The interconnection line layout may include layouts (e.g., via patternsV0) for via patterns, layouts (e.g., conductive lines M1 a-M1 g) forinterconnection lines, and layouts (e.g., power lines PM1 and PM2) forpower interconnection lines. Each of the first and second power linesPM1 and PM2 may be a line-shaped structure extending in the seconddirection D2. The first and second power lines PM1 and PM2 may beconnected to some of the active contact patterns CAa-CAl through the viapatterns V0. The conductive lines M1 a-M1 g may be connected to some ofthe connection patterns M0 a-M0 h, some of the active contact patternsCAa-CAl, and some of the gate contact patterns CBa-CBh through the viapatterns V0.

The first standard cell layout STD1 will now be described. For example,first active contact patterns CAa may be provided to be overlapped withthe first and second power lines PM1 and PM2, respectively. The firstand second power lines PM1 and PM2 may be respectively connected to thefirst active contact patterns CAa through the via patterns V0. A firstgate contact pattern CBa may be provided to be overlapped with at leastone of the gate patterns GP. The first conductive line M1 a may beconnected to the first gate contact pattern CBa through the via patternV0.

A pair of first conductive patterns CL1 may be disposed to be adjacentto the first conductive line M1 a. The pair of first conductive patternsCL1 may be disposed on the PMOSFET region PR and the NMOSFET region NR,respectively. Each of the first conductive patterns CL1 may include asecond active contact pattern CAb and a first connection pattern M0 a.The second active contact pattern CAb and the first connection patternM0 a may be partially overlapped with each other. A second conductiveline M1 b may be connected to the pair of first conductive patterns CL1,respectively, through the via patterns V0.

A pair of second conductive patterns CL2 may be disposed on a boundarybetween the first standard cell layout STD1 and the second standard celllayout STD2. The pair of second conductive patterns CL2 may be disposedon the PMOSFET region PR and the NMOSFET region NR, respectively. Eachof the second conductive patterns CL2 may include a second gate contactpattern CBb, a second connection pattern M0 b, and a third activecontact pattern CAc. The second gate contact pattern CBb may beoverlapped with the second connection pattern M0 b. The third activecontact pattern CAc and the second connection pattern M0 b may bepartially overlapped with each other. However, the second gate contactpattern CBb and the third active contact pattern CAc may be spaced apartfrom each other in the second direction D2. The first and second powerlines PM1 and PM2 may be connected to the pair of second conductivepatterns CL2, respectively, through the via patterns V0.

The second standard cell layout STD2 will now be described. A pair ofthird conductive patterns CL3 may be disposed on the substrate 100. Thepair of third conductive patterns CL3 may be disposed on the PMOSFETregion PR and the NMOSFET region NR, respectively. Each of the thirdconductive patterns CL3 may include a fourth active contact pattern CAd,a fifth active contact pattern CAe, and a third connection pattern M0 c.The fourth and fifth active contact patterns CAd and CAe may be spacedapart from each other in the second direction D2 with the gate patternGP interposed therebetween. The third connection pattern M0 c may crossthe gate pattern GP and extend in the second direction D2. The fourthactive contact pattern CAd and the third connection pattern M0 c may bepartially overlapped with each other, and the fifth active contactpattern CAe and the third connection pattern M0 c may be partiallyoverlapped with each other.

A fourth conductive pattern CL4 may be disposed to be adjacent to thepair of third conductive patterns CL3. The fourth conductive pattern CL4may be disposed between the PMOSFET region PR and the NMOSFET region NR.The fourth conductive pattern CL4 may include a third gate contactpattern CBc, a fourth gate contact pattern CBd, and a fourth connectionpattern M0 d. The third and fourth gate contact patterns CBc and CBd mayeach be overlapped with adjacent gate patterns GP. The fourth connectionpattern M0 d may cross the gate patterns GP and extend in the seconddirection D2. The third and fourth gate contact patterns CBc and CBd maybe overlapped with the fourth connection pattern M0 d. A thirdconductive line M1 c may be connected to the fourth conductive patternCL4 through the via pattern V0.

A pair of sixth active contact patterns CAf may be disposed between thegate patterns GP connected to the third and fourth gate contact patternsCBc and CBd, respectively. The pair of sixth active contact patterns CAfmay be disposed on the PMOSFET region PR and the NMOSFET region NR,respectively. A fourth conductive line M1 d may be connected to the pairof sixth active contact patterns CAf through the via patterns V0.

If the fourth connection pattern M0 d is omitted, the third and fourthconductive lines M1 c and M1 d may not be formed in the shapes andpositions shown in FIG. 13. For example, the first and second conductivelines M1 a and M1 b may have shapes and positions similar to those shownin FIG. 14B.

A pair of fifth conductive patterns CL5 may be disposed on a boundarybetween the second standard cell layout STD2 and the third standard celllayout STD3. The pair of fifth conductive patterns CL5 may be disposedon the PMOSFET region PR and the NMOSFET region NR, respectively. Eachof the fifth conductive patterns CL5 may include a seventh activecontact pattern CAg, a fifth connection pattern M0 e, a fifth gatecontact pattern CBe, and an eighth active contact pattern CAh. The fifthgate contact pattern CBe may be overlapped with the fifth connectionpattern M0 e. The seventh active contact pattern CAg and the fifthconnection pattern M0 e may be partially overlapped with each other, andthe eighth active contact pattern CAh and the fifth connection patternM0 e may be partially overlapped with each other. The seventh and eighthactive contact patterns CAg and CAh and the fifth gate contact patternCBe may be spaced apart from each other in the second direction D2. Theeighth active contact pattern CAh may extend in the first direction D1and may be partially overlapped with the power lines PM1 and PM2. Thefirst and second power lines PM1 and PM2 may be connected to the pair offifth conductive patterns CL5, respectively, through the via patternsV0.

The third standard cell layout STD3 will now be described. For example,a sixth gate contact pattern CBf and a seventh gate contact pattern CBgmay be provided on the substrate 100. The sixth and seventh gate contactpatterns CBf and CBg may be disposed between the PMOSFET region PR andthe NMOSFET region NR. The sixth and seventh gate contact patterns CBfand CBg may be respectively overlapped with the gate patterns GP thatare adjacent to each other. Furthermore, the sixth and seventh gatecontact patterns CBf and CBg may be overlapped with a fifth conductiveline M1 e. The fifth conductive line M1 e may include a first portion,which is overlapped with the sixth and seventh gate contact patterns CBfand CBg and extends in the second direction D2, and a second portionextending in the first direction D1. The fifth conductive line M1 e maybe connected to the sixth and seventh gate contact patterns CBf and CBgthrough the via patterns V0.

A sixth conductive pattern CL6 may be disposed to be adjacent to thefifth conductive line M1 e. The sixth conductive pattern CL6 may bedisposed between the PMOSFET region PR and the NMOSFET region NR. Thesixth conductive pattern CL6 may include an eighth gate contact patternCBh and a sixth connection pattern M0 f. The eighth gate contact patternCBh may extend in the second direction D2 and may be overlapped with apair of the gate patterns GP that are adjacent to each other. The sixthconnection pattern M0 f may include a first portion, which extends inthe second direction D2 and is overlapped with the eighth gate contactpattern CBh, and a second portion extending in the first direction D1.The second portion of the sixth connection pattern M0 f may beoverlapped with the sixth conductive line M1 f. The sixth conductiveline M1 f may be connected to the sixth conductive pattern CL6 throughthe via pattern V0.

A seventh conductive pattern CL7 may be provided on the NMOSFET regionNR. The seventh conductive pattern CL7 may include a ninth activecontact pattern CAi, a tenth active contact pattern CAj, and a seventhconnection pattern M0 g. The ninth and tenth active contact patterns CAiand CAj may be spaced apart from each other in the second direction D2with the gate patterns GP interposed therebetween. The seventhconnection pattern M0 g may include a first portion, which extends inthe first direction D1 and is overlapped with the ninth active contactpattern CAi, a second portion, which extends in the first direction D1and is overlapped with the tenth active contact pattern CAj, and a thirdportion, which extends in the second direction D2 and crosses the gatepatterns GP.

An eighth conductive pattern CL8 may be disposed to be adjacent to thesixth conductive pattern CL6. The eighth conductive pattern CL8 mayextend from the PMOSFET region PR to the NMOSFET region NR. The eighthconductive pattern CL8 may include an eleventh active contact patternCAk, a twelfth active contact pattern CAl, and an eighth connectionpattern M0 h. The eleventh and twelfth active contact patterns CAk andCAl may be disposed on the PMOSFET region PR and the NMOSFET region NR,respectively. The eleventh active contact pattern CAk may be overlappedwith the sixth conductive line M1 f. The eighth connection pattern M0 hmay include a first portion, which extends in the second direction D2and is overlapped with the eleventh active contact pattern CAk, a secondportion, which extends in the second direction D2 and is overlapped withthe twelfth active contact pattern CAl, and a third portion, whichextends in the first direction D and connects the first and secondportions to each other. The first portion of the eighth connectionpattern M0 h may cross at least one of the gate patterns GP.Furthermore, the eighth connection pattern M0 h and a seventh conductiveline M1 g may be partially overlapped with each other. The seventhconductive line M1 g may be connected to the eighth connection patternM0 h through the via pattern V0.

In the pair of first conductive patterns CL1 described above, a pair ofthe second active contact patterns CAb may be connected to each otherthrough the first connection patterns M0 a and the second conductiveline M1 b. In the eighth conductive pattern CL8, the eleventh andtwelfth active contact patterns CAk and CAl may be electricallyconnected to each other through only the eighth connection pattern M0 h.

So far, examples of the first to eighth conductive patterns CL1-CL8,which are disposed on the first to third standard cell layouts STD1,STD2, and STD3, have been described. However, the inventive concept maynot be limited thereto. For example, the active contact patterns, thegate contact patterns, and the connection patterns may be changed interms of their shapes and positions and may be connected to each otherin various manners.

FIG. 14A is a layout diagram illustrating a region ‘M’ of FIG. 13according to exemplary embodiments of the present inventive concept.FIG. 14B is a layout diagram illustrating the region ‘M’ of FIG. 13according to a comparative example.

Referring to FIG. 14A, the first gate contact pattern CBa, the pair offirst conductive patterns CL1, and the first and second conductive linesM1 a and M1 b that have been previously described with reference to FIG.13 may be disposed on the substrate 100. The first conductive line M1 amay be connected to the first gate contact pattern CBa through a viapattern V0. Each of the first conductive patterns CL1 may include asecond active contact pattern CAb and a first connection pattern M0 a.The first connection pattern M0 a and the second conductive line M1 bmay be partially overlapped with each other. Accordingly, the secondconductive line M1 b may be connected to the pair of the firstconnection patterns M0 a through the via patterns V0.

Each of the first and second conductive lines M1 a and M1 b may includepin regions PI for establishing routing paths to upper interconnectionlines. As an example, each of the first and second conductive lines M1 aand M1 b may include five pin regions PI, which are arranged parallel toits longitudinal axis or in the first direction D1. In other words, thefirst and second conductive lines M1 a and M1 b may include ten pinregions PI.

Referring to FIG. 14B, a first gate contact pattern CBa, a pair ofsecond active contact patterns CAb, and first and second conductivelines M1 a and M1 b may be disposed on a substrate. However, unlike thatof FIG. 14A, the first connection patterns M0 a are not included. Thesecond conductive line M1 b may include a first portion extending in afirst direction D1 and second portions, which extend in a seconddirection D2 and are overlapped with the pair of second active contactpatterns CAb, respectively. The second conductive line M1 b may beconnected to the pair of second active contact patterns CAb through viapatterns V0.

Each of the first and second conductive lines M1 a and M1 b may includepin regions PI for establishing routing paths to upper interconnectionlines. Due to the second portions of the second conductive line M1 b, alength of the first conductive line M1 a in the first direction D1 maybe shorter than that of the first conductive line M1 a of FIG. 14A.Thus, the first conductive line M1 a may include, for example, three pinregions PI, and the second conductive line M1 b may include five pinregions PI. As a result, the first and second conductive lines M1 a andM1 b may include eight pin regions PI. In other words, the number of thepin regions PI on the first and second conductive lines M1 a and M1 bmay be less than that in the embodiment described with reference to FIG.14A.

FIG. 15A is a layout diagram illustrating a region ‘N’ of FIG. 13according to exemplary embodiments of the present inventive concept.FIG. 15B is a layout diagram illustrating the region ‘N’ of FIG. 13according to a comparative example.

Referring to FIG. 15A, the sixth conductive pattern CL6, the eighthconductive pattern CL8, and the sixth and seventh conductive lines M1 fand M1 g previously described with reference to FIG. 13 may be disposedon the substrate 100. The sixth conductive pattern CL6 may include aneighth gate contact pattern CBh and a sixth connection pattern M0 f. Theeighth conductive pattern CL8 may include an eleventh active contactpattern CAk, a twelfth active contact pattern CAl, and an eighthconnection pattern M0 h. The sixth connection pattern M0 f and the sixthconductive line M1 f may be partially overlapped with each other, andthe eighth connection pattern M0 h and the seventh conductive line M1 gmay be partially overlapped with each other. Accordingly, the sixthconductive line M1 f may be connected to the sixth connection pattern M0f through the via pattern V0, and the seventh conductive line M1 g maybe connected to the eighth connection pattern M0 h through the viapattern V0.

Each of the sixth and seventh conductive lines M1 f and M1 g may includepin regions PI for establishing routing paths to upper interconnectionlines. As an example, each of the sixth and seventh conductive lines M1f and M1 g may include five pin regions PI, which are arranged parallelto its longitudinal axis or in the first direction D1. In other words,the sixth and seventh conductive lines M1 f and M1 g may include ten pinregions PI.

Referring to FIG. 15B, a sixth conductive pattern CL6, an eleventhactive contact pattern CAk, a twelfth active contact pattern CAl, andsixth and seventh conductive lines M1 f and M1 g may be disposed on asubstrate. However, unlike that of FIG. 15A, the eighth connectionpattern M0 h is not included. The seventh conductive line M1 g mayinclude a first portion extending in a first direction D1 and secondportions, which extend in a second direction D2 and are overlapped withthe eleventh and twelfth active contact patterns CAk and CAl,respectively. The seventh conductive line M1 g may be connected to eachof the eleventh and twelfth active contact patterns CAk and CAl throughvia patterns V0.

Each of the sixth and seventh conductive lines M1 f and M1 g may includepin regions PI for establishing routing paths to upper interconnectionlines. Due to the second portions of the seventh conductive line M1 g, alength of the sixth conductive line M1 f in the first direction D1 maybe shorter than that of the sixth conductive line M1 f of FIG. 15A.Thus, the sixth conductive line M1 f may include, for example, three pinregions PI, and the seventh conductive line M1 g may include five pinregions PI. As a result, the sixth and seventh conductive lines M1 f andM1 g may include eight pin regions PI. In other words, the number of thepin regions PI on the sixth and seventh conductive lines M1 f and M1 gmay be less than that in the embodiment described with reference to FIG.15A.

As described with reference to FIGS. 14 and 15, a standard cell layoutaccording to exemplary embodiments of the present inventive concept mayinclude an additional connection pattern, as well as an active contactpattern and a gate contact pattern. Thus, it is possible to increase adegree of freedom in placing a layout for interconnection lines orconductive lines and to increase an area of pin regions for establishingrouting paths to upper interconnection lines. In other words, theconnection pattern makes it possible to more easily construct a routingstructure.

FIG. 16 is a plan view illustrating a semiconductor device according toexemplary embodiments of the present inventive concept. FIGS. 17Athrough 17R are sectional views taken along lines A-A′, B-B′, C-C′,D-D′, E-E′, F-F′, G-G′, H-H′, I-I′, J-J′, K-K′, L-L′, M-M′, N-N′, O-O′,P-P′, Q-Q′, and R-R′, respectively, of FIG. 16. For example, FIG. 16 andFIGS. 17A through 17R illustrate an example of a semiconductor devicethat is formed based on the standard cell layouts of FIG. 13. In thefollowing description of the present embodiment, an element previouslydescribed with reference to FIGS. 4, 6, 8, 10, and 12 may not bedescribed in much further detail for the sake of brevity.

In a semiconductor device to be described with reference to FIGS. 16 and17A to 17R, each element of the semiconductor device may be integratedon a semiconductor substrate 100 through the photolithography processS150 of FIG. 2, and thus, they may not be identical to correspondingpatterns constituting the standard cell layout of FIG. 13. Thesemiconductor device may be, for example, a system-on-chip.

Referring to FIGS. 16 and 17A to 17R, second device isolation patternsST2 may be provided on a substrate 100 to define a PMOSFET region PR andan NMOSFET region NR. The second device isolation patterns ST2 may beprovided in an upper portion of the substrate 100. In exemplaryembodiments of the present inventive concept, the substrate 100 may be asilicon substrate, a germanium substrate, or a silicon-on-insulator(SOI) substrate.

The PMOSFET and NMOSFET regions PR and NR may be spaced apart from eachother, in a first direction D1 parallel to a top surface of thesubstrate 100, by the second device isolation patterns ST2 interposedtherebetween. Although each of the PMOSFET and NMOSFET regions PR and NRis illustrated to be a single region, each of the PMOSFET and NMOSFETregions PR and NR may include a plurality of regions spaced apart fromeach other by the second device isolation patterns ST2.

A plurality of first active patterns FN1 may be provided on the PMOSFETregion PR to extend in a second direction D2 crossing the firstdirection D1, and a plurality of second active patterns FN2 may beprovided on the NMOSFET region NR to extend in the second direction D2.The first and second active patterns FN1 and FN2 may be parts of thesubstrate 100 and may have a protruding shape. In other words, they mayprotrude from the substrate 100. The first and second active patternsFN1 and FN2 may be arranged in the first direction D1. First deviceisolation patterns ST1 extending in the second direction D2 may bedisposed at both sides of each of the first and second active patternsFN1 and FN2.

Between the first device isolation patterns ST1, upper portions of thefirst and second active patterns FN1 and FN2 may vertically protrudewith respect to the first device isolation patterns ST1. In other words,each of the upper portions of the first and second active patterns FN1and FN2 may have a fin-shaped structure, between the first deviceisolation patterns ST1.

The second device isolation patterns ST2 may be substantially connectedto the first device isolation patterns ST1 to form a single insulatingpattern. The second device isolation patterns ST2 may be thicker thanthe first device isolation patterns ST1. In this case, the first deviceisolation patterns ST1 and the second device isolation patterns ST2 maybe formed by different processes. As an example, the first and seconddevice isolation patterns ST1 and ST2 may be formed of or include asilicon oxide layer.

Gate electrodes GE may be provided on the first and second activepatterns FN1 and FN2 to extend in the first direction D1 and to crossthe first and second active patterns FN1 and FN2. The gate electrodes GEmay be spaced apart from each other in the second direction D2. Each ofthe gate electrodes GE may extend in the first direction D1 and crossthe PMOSFET region PR, the second device isolation patterns ST2, and theNMOSFET region NR.

In exemplary embodiments of the present inventive concept, dummy gateelectrodes DM may be respectively provided on a boundary between a firststandard cell STDC1 and a second standard cell STDC2 and on a boundarybetween the second standard cell STDC2 and a third standard cell STDC3.Each of the dummy gate electrodes DM may be divided into two electrodes,by the second device isolation pattern ST2, but the present inventiveconcept may not be limited thereto. The dummy gate electrodes DM mayhave substantially the same structure as the gate electrodes GE and maybe formed of substantially the same material as the gate electrodes GE.In a circuit, the dummy gate electrodes DM may serve as a conductiveline, of a transistor.

A gate insulating pattern GI may be provided below each of the gateelectrodes GE, and gate spacers GS may be provided at both sides of eachof the gate electrodes GE. Furthermore, a capping pattern CP may beprovided to cover a top surface of each of the gate electrodes GE.However, in exemplary embodiments of the present inventive concept, thecapping pattern CP may be partially removed from a portion of the topsurface of the gate electrode GE, to which a gate contact GC to bedescribed below is connected. The gate insulating pattern GI may bevertically extended to cover both sidewalls of the gate electrode GE.For example, the gate insulating pattern GI may be interposed betweenthe gate electrode GE and the gate spacer GS. First to third interlayerinsulating layers 110-130 may be provided to cover the first and secondactive patterns FN1 and FN2 and the gate electrodes GE.

The gate electrodes GE may be formed of or include doped semiconductormaterials, conductive metal nitrides, or metals. The gate insulatingpattern GI may be formed of or include a silicon oxide layer, a siliconoxynitride layer, or high-k dielectric materials, whose dielectricconstants are lower than that of silicon oxide. Each of the cappingpattern CP and the gate spacers GS may include a silicon oxide layer, asilicon nitride layer, or a silicon oxynitride layer. Each of the firstto third interlayer insulating layers 110-130 may include a siliconoxide layer or a silicon oxynitride layer.

Source/drain regions SD may be provided on or in the upper portions ofthe first and second active patterns FN1 and FN2. The source/drainregions SD on the PMOSFET region PR may be p-type impurity regions, andthe source/drain regions SD on the NMOSFET region NR may be n-typeimpurity regions. Channel regions AF may be provided in the upperportion of each of the first and second active patterns FN1 and FN2 thatare overlapped with the gate electrodes GE, respectively. Each of thechannel regions AF may be interposed between the source/drain regionsSD.

The source/drain regions SD may be epitaxial patterns formed by aselective epitaxial growth process. Accordingly, the source/drainregions SD may have top surfaces positioned at a higher level than thoseof the channel regions AF. The source/drain regions SD may include asemiconductor element different from those of the substrate 100. As anexample, the source/drain regions SD may be formed of or include asemiconductor material having a lattice constant different from (forexample, greater or smaller than) the substrate 100. Accordingly, thesource/drain regions SD may exert a compressive stress or a tensilestress on the channel regions AF.

Lower conductive structures TS may be provided on the PMOSFET andNMOSFET regions PR and NR between the gate electrodes GE. The lowerconductive structures TS may be a pattern that is formed in accordancewith the lower conductive patterns LP of FIG. 13. The lower conductivestructures TS may be provided in the first interlayer insulating layer110 and may be directly connected to the source/drain regions SD. Thelower conductive structures TS may extend in the first direction D1.Each of the lower conductive structures TS may be partially overlappedwith a first or second power interconnection line PL1 or PL2, whenviewed in a plan view. The lower conductive structures TS may have topsurfaces that are substantially coplanar with that of the firstinterlayer insulating layer 110. In the present embodiment, each of thelower conductive structures TS are illustrated to be in contact with aplurality of the source/drain regions SD, but the present inventiveconcept may not be limited thereto. As an example, at least one of thelower conductive structures TS may be in contact with one or two of thesource/drain regions SD. The lower conductive structures TS may beformed of or include doped semiconductor materials, conductive metalnitrides, metals, or metal silicides.

Conductive structures GC, AC, and CP1-CP8 may be provided in the secondinterlayer insulating layer 120. The conductive structures GC, AC, andCP1-CP8 may include gate contacts GC, active contacts AC, and first toeighth conductive structures CP1-CP8. The conductive structures GC, AC,and CP1-CP8 may be patterns that are formed in accordance with theconnection patterns M0 a-M0 h, the active contact patterns CAa-CAl, andthe gate contact patterns CBa-CBh of FIG. 13. The conductive structuresGC, AC, and CP1-CP8 may include conductive metal nitrides or metals.

The conductive structures GC, AC, and CP1-CP8 may have top surfaces thatare substantially coplanar with that of the second interlayer insulatinglayer 120. In addition, the active contacts AC may have bottom surfacesthat are substantially coplanar with that of the second interlayerinsulating layer 120. The bottom surfaces of the gate contacts GC may belower than that of the second interlayer insulating layer 120. In otherwords, the bottom surfaces of the gate contacts GC may be lower thanthose of the active contacts AC. The first to eighth conductivestructures CP1-CP8 will be described in more detail below.

Barrier patterns BL may be respectively interposed between the secondinterlayered insulating layer 120 and the conductive structures GC, AC,and CP1-CP8. The barrier pattern BL may directly cover side and bottomsurfaces of the conductive structures GC, AC, and CP1-CP8, except fortop surfaces thereof. The barrier patterns BL may include a metalnitride for preventing metallic elements in the conductive structuresGC, AC, and CP1-CP8 from being diffused. For example, the barrierpatterns BL may be formed of or include TiN.

First and second power interconnection lines PL1 and PL2 and first tosixth interconnection lines ML1-ML6 may be provided in the thirdinterlayer insulating layer 130. The first and second powerinterconnection lines PL1 and PL2 may be patterns that are formed inaccordance with the power lines PM1 and PM2 of FIG. 13, and the first tosixth interconnection lines ML1-ML6 may be patterns that are formed inaccordance with the conductive lines M1 a-M1 f of FIG. 13.

Each of the first and second power interconnection lines PL1 and PL2 andeach of the first to sixth interconnection lines ML1-ML6 may include aline portion LI extending parallel to the top surface of the substrate100 and a contact portion VI, which is vertically connected to theconductive structures GC, AC, and CP1-CP8. The contact portion VI may bea pattern that is formed in accordance with the via pattern V0 of FIG.13.

Barrier patterns BL may be respectively interposed between the thirdinterlayer insulating layer 130 and the first and second powerinterconnection lines PL1 and PL2 and between the third interlayerinsulating layer 130 and the first to sixth interconnection linesML1-ML6. The barrier patterns BL may include a metal nitride forpreventing metallic elements from being diffused. For example, thebarrier patterns BL may be formed of or include TiN.

The first standard cell STDC1 will be described with reference to FIGS.16 and 17A to 17E. A pair of the active contacts AC may be provided onthe lower conductive structures TS disposed below the first or secondpower interconnection line PL1 or PL2. In other words, when viewed in asectional view, the pair of active contacts AC may be interposed betweenthe first or second power interconnection line PL1 and PL2 and the lowerconductive structures TS. The pair of active contacts AC may be patternsthat are formed in accordance with the pair of first active contactpatterns CAa of FIG. 13. The pair of active contacts AC may beelectrically connected to the first and second power interconnectionlines PL1 and PL2. A power or ground voltage applied to the first andsecond power interconnection lines PL1 and PL2 may be applied to thelower conductive structures TS through the pair of active contacts AC(e.g., see FIG. 17D). Here, since, when viewed in a plan view, the lowerconductive structures TS may be overlapped with the first and secondpower interconnection lines PL1 and PL2, the power or ground voltage maybe applied to the lower conductive structures TS through a vertical andstraight current path.

The gate contact GC may be provided on at least one gate electrode GE ofthe first standard cell STDC1. The gate contact GC may be provided onthe second device isolation pattern ST2 between the PMOSFET region PRand the NMOSFET region NR. The gate contact GC may be a pattern that isformed in accordance with the first gate contact pattern CBa of FIG. 13.The first interconnection line ML1 may be provided on and connected tothe gate contact GC. For example, the first interconnection line ML1 andthe gate electrode GE may be electrically connected to each otherthrough the gate contact GC.

A pair of the first conductive structures CP1 may be provided on thePMOSFET region PR and the NMOSFET region NR of the first standard cellSTDC1, respectively. The pair of first conductive structures CP1 may bepatterns that are formed in accordance with the pair of first conductivepatterns CL1 of FIG. 13. Each of the first conductive structures CP1 mayinclude a first portion P1 and a second portion P2.

The first portion P1 may be a pattern that is formed in accordance withthe first connection pattern M0 a of FIG. 13, and the second portion P2may be a pattern that is formed in accordance with the second activecontact pattern CAb of FIG. 13. For example, the second portion P2 maybe connected to the lower conductive structure TS, and the first portionP1 may extend from the second portion P2 in a direction parallel to atop surface of the substrate 100.

The first conductive structures CP1 may be similar to the conductivestructure CP previously described with reference to FIG. 4. However, thesemiconductor device according to the present embodiment may furtherinclude the lower conductive structure TS provided between the activeregions AR and the first conductive structures CP1. For example, thefirst portion P1 and the second portion P2 may have top surfaces thatare substantially coplanar with each other, but a bottom surface of thefirst portion P1 may be higher than that of the second portion P2. Thebottom surface of the second portion P2 may be positioned atsubstantially the same height as those of the active contacts AC.

The second interconnection line ML2 may be provided on and connected tothe first conductive structures CP1. In other words, the secondinterconnection line ML2 and the lower conductive structures TS may beelectrically connected to each other through the first conductivestructures CP1. In addition, the source/drain regions SD on the PMOSFETregion PR may be electrically connected to the source/drain regions SDon the NMOSFET region NR through the lower conductive structures TS, thefirst conductive structures CP1, and the second interconnection lineML2.

The second conductive structures CP2 provided at an interface betweenthe first standard cell STDC1 and the second standard cell STDC2 will bedescribed with reference to FIGS. 16 and 17F to 17H. A pair of thesecond conductive structures CP2 may be provided on the PMOSFET regionPR and the NMOSFET region NR, respectively. The pair of secondconductive structures CP2 may be patterns that are formed in accordancewith the pair of second conductive patterns CL2 of FIG. 13. Each of thesecond conductive structures CP2 may include a first portion P1, asecond portion P2, and a third portion P3.

The first portion P1 may be a pattern that is formed in accordance withthe second connection pattern M0 b of FIG. 13, the second portion P2 maybe a pattern that is formed in accordance with the third active contactpattern CAc of FIG. 13, and the third portion P3 may be a pattern thatis formed in accordance with the second gate contact pattern CBb of FIG.13. For example, the second portion P2 may be connected to the lowerconductive structure TS, and the third portion P3 may be connected tothe gate electrode GE. The first portion P1 may extend in a directionparallel to a top surface of the substrate 100 and connect the secondportion P2 and the third portion P3 to each other.

The second conductive structures CP2 may be similar to the conductivestructure CP previously described with reference to FIG. 8. For example,the first portion P1, the second portion P2, and the third portion P3may have top surfaces that are substantially coplanar with each other.However, the first portion P1, the second portion P2, and the thirdportion P3 may have bottom surfaces that are positioned at differentheights. For example, the bottom surface of the second portion P2 may behigher than that of the third portion P3, and the bottom surface of thefirst portion P1 may be higher than that of the second portion P2. Thebottom surface of the third portion P3 may be positioned at the sameheight as bottom surfaces of the gate contacts GC.

The first and second power interconnection lines PL1 and PL2 may beconnected to the second conductive structures CP2, respectively, throughthe second portions P2. In other words, the first and second powerinterconnection lines PL1 and PL2 may be electrically connected to thelower conductive structures TS and the gate electrodes GE through thesecond conductive structures CP2.

The second standard cell STDC2 will be described with reference to FIGS.16 and 17I to 17M. A pair of the third conductive structures CP3 may beprovided to be adjacent to each of the pair of second conductivestructures CP2. The pair of third conductive structures CP3 may beprovided on the PMOSFET region PR and the NMOSFET region NR,respectively. The pair of third conductive structures CP3 may bepatterns that are formed in accordance with the pair of third conductivepatterns CL3 of FIG. 13. Each of the third conductive structures CP3 mayinclude a first portion P1 and a pair of second portions P2.

The first portion P1 may be a pattern that is formed in accordance withthe third connection pattern M0 c of FIG. 13, and the second portions P2may be patterns that are respectively formed in accordance with thefourth active contact pattern CAd and the fifth active contact patternCAe of FIG. 13. For example, the pair of second portions P2 may berespectively connected to a pair of the lower conductive structures TS,which are disposed to be adjacent to each other with the gate electrodeGE interposed therebetween. The first portion P1 may extend parallel tothe top surface of the substrate 100 and may connect the second portionsP2 to each other.

The third conductive structures CP3 may be similar to the conductivestructure CP previously described with reference to FIG. 10. Forexample, the first portion P1 and the second portions P2 may have topsurfaces that are substantially coplanar with each other, but a bottomsurface of the first portion P1 may be higher than that of the secondportions P2. Since the bottom surface of the first portion P1 is higherthan top surfaces of the lower conductive structures TS and a topsurface of the gate electrode GE, the third conductive structure CP3 mayelectrically connect the lower conductive structures TS, which arespaced apart from each other in the second direction D2, to each other.This way, the gate electrode GE is not short circuited. In other words,the third conductive structures CP3 may each serve as a jumper forelectrically connecting the source/drain regions SD that are separatedfrom each other in the second direction D2.

A fourth conductive structure CP4 may be provided on an adjacent pair ofthe gate electrodes GE of the second standard cell STDC2. The fourthconductive structure CP4 may be provided on a second device isolationpattern ST2 between the PMOSFET and NMOSFET regions PR and NR. Thefourth conductive structure CP4 may be a pattern that is formed inaccordance with the fourth conductive pattern CL4 of FIG. 13. The fourthconductive structure CP4 may include a first portion P1 and a pair ofthird portions P3.

The first portion P1 may be a pattern that is formed in accordance withthe fourth connection pattern M0 d of FIG. 13, and the third portions P3may be patterns that are respectively formed in accordance with thethird gate contact pattern CBc and the fourth gate contact pattern CBdof FIG. 13. For example, the pair of third portions P3 may be connectedto the pair of gate electrodes GE, respectively. The first portion P1may extend parallel to the top surface of the substrate 100 and mayconnect the third portions P3 to each other.

The fourth conductive structure CP4 may be similar to the conductivestructure CP previously described with reference to FIG. 12. Forexample, the first portion P1 and the third portions P3 may have topsurfaces that are substantially coplanar with each other, but a bottomsurface of the first portion P1 may be higher than that of the thirdportions P3. Since the bottom surface of the first portion P1 is higherthan the top surfaces of the lower conductive structures TS, the thirdconductive structure CP3 may connect the pair of gate electrodes GEelectrically to each other, without shorting the lower conductivestructures TS adjacent thereto.

The third interconnection line ML3 may be provided on and connected tothe fourth conductive structure CP4. When viewed in a plan view, thethird interconnection line ML3 may be spaced apart from the pair of gateelectrodes GE in the second direction D2. When the third interconnectionline ML3 is not overlapped with at least one of the pair of gateelectrodes GE in a plan view, the third interconnection line ML3 may beelectrically connected to the pair of gate electrodes GE through thefirst portion P1.

A pair of the active contacts AC may be respectively provided on thePMOSFET region PR and the NMOSFET region NR to be adjacent to the fourthconductive structure CP4. The pair of active contacts AC may be patternsthat are formed in accordance with the pair of sixth active contactpatterns CAf of FIG. 13.

The fourth interconnection line ML4 may be provided on and connected tothe pair of active contacts AC. When viewed in a plan view, the fourthinterconnection line ML4 may cross the fourth conductive structure CP4and extend in the first direction D1. Since a bottom surface of the lineportion LI of the fourth interconnection line ML4 is higher than a topsurface of the fourth conductive structure CP4, the fourthinterconnection line ML4 may be vertically separated from the fourthconductive structure CP4.

The fifth conductive structures CP5, which are provided at an interfacebetween the second standard cell STDC2 and the third standard cellSTDC3, will be described with reference to FIGS. 16 and 17N. A pair ofthe fifth conductive structures CP5 may be provided on the PMOSFETregion PR and the NMOSFET region NR, respectively. The pair of fifthconductive structures CP5 may be patterns that are formed in accordancewith the pair of fifth conductive patterns CL5 of FIG. 13. Each of thefifth conductive structures CP5 may include a first portion P1, secondportions P2, and a third portion P3.

The first portion P1 may be a pattern that is formed in accordance withthe fifth connection pattern M0 e of FIG. 13, the second portions P2 maybe patterns that are respectively formed in accordance with the seventhactive contact pattern CAg and the eighth active contact pattern CAh ofFIG. 13, and the third portion P3 may be a pattern that is formed inaccordance with the fifth gate contact pattern CBe of FIG. 13. Forexample, the second portions P2 may be connected to a pair of the lowerconductive structures TS that are adjacent to each other, and the thirdportion P3 may be connected to the gate electrode GE between the pair oflower conductive structures TS. In other words, when viewed in a planview, the third portion P3 may be interposed between the second portionsP2. One of the second portions P2 may extend farther in the firstdirection D1, compared with the other, and thus, it may be overlappedwith the first or second power interconnection line PL1 and PL2, whenviewed in a plan view. The first portion P1 may extend the seconddirection D2 and may connect the second portions P2 and the thirdportion P3 to each other. Except that a plurality of second portions P2are provided, the fifth conductive structures CP5 may be similar to thesecond conductive structures CP2 described above.

The third standard cell STDC3 will be described with reference to FIGS.16 and 17O to 17R. A first gate group GG1 and a second gate group GG2may be provided on the third standard cell STDC3. Each of the first andsecond gate groups GG1 and GG2 may include a pair of the gate electrodesGE that are disposed to be adjacent to each other. Furthermore, thefirst gate group GG1 and the second gate group GG2 may be adjacent toeach other.

A pair of the gate contacts GC may be provided on the pair of gateelectrodes GE, respectively, of the first gate group GG1. Furthermore, asixth conductive structure CP6 may be provided on the second gate groupGG2. The pair of gate contacts GC may be patterns that are respectivelyformed in accordance with the sixth gate contact pattern CBf and theseventh gate contact pattern CBg of FIG. 13. The sixth conductivestructure CP6 may be a pattern that is formed in accordance with thesixth conductive pattern CL6 of FIG. 13. The sixth conductive structureCP6 may include a first portion P1 and a third portion P3.

The first portion P1 may be a pattern that is formed in accordance withthe sixth connection pattern M0 f of FIG. 13, and the third portion P3may be a pattern that is formed in accordance with the eighth gatecontact pattern CBh of FIG. 13. The third portion P3 may extend in thesecond direction D2 and may be connected to both of the pair of gateelectrodes GE of the second gate group GG2. The first portion P1 of thesixth conductive structure CP6 may include a first extended portion HP1extending in the second direction D2 and a second extended portion HP2extending in the first direction D1. The first extended portion HP1 maybe overlapped with the third portion P3. In this case, the firstextended portion HP1 and the third portion P3 may be connected to eachother to constitute a single body.

A fifth interconnection line ML5 may be provided on the pair of gatecontacts GC, and a sixth interconnection line ML6 may be provided on thesixth conductive structure CP6. The fifth interconnection line ML5 mayinclude a first region extending in the first direction D1 and a secondregion extending from the first region in the second direction D2. Thesecond region of the fifth interconnection line ML5 may be overlappedwith the pair of gate contacts GC, when viewed in a plan view. The fifthinterconnection line ML5 may be connected to the pair of gate contactsGC through the second region.

The second extended portion HP2 of the sixth conductive structure CP6may be partially overlapped with the sixth interconnection line ML6,when viewed in a plan view. The sixth interconnection line ML6 may beconnected to the sixth conductive structure CP6 through the secondextended portion HP2.

A seventh conductive structure CP7 may be provided on the NMOSFET regionNR to be adjacent to the pair of gate contacts GC and the sixthconductive structure CP6. The seventh conductive structure CP7 may be apattern that is formed in accordance with the seventh conductive patternCL7 of FIG. 13. The seventh conductive structure CP7 may include a firstportion P1 and a pair of second portions P2. The seventh conductivestructure CP7 may be similar to the third conductive structure CP3described above.

The first portion P1 may be a pattern that is formed in accordance withthe seventh connection pattern M0 g of FIG. 13, and the second portionsP2 may be patterns that are respectively formed in accordance with theninth active contact pattern CAi and the tenth active contact patternCAj of FIG. 13. The second portions P2 may be spaced apart from eachother with at least one of the gate electrodes GE interposedtherebetween. The first portion P1 of the seventh conductive structureCP7 may include a first extended portion HP1 extending in the seconddirection D2 and a pair of second extended portions HP2 extending in thefirst direction D1. The pair of second extended portions HP2 may beoverlapped with the pair of second portions P2, respectively. In otherwords, the first portion P1 may connect the pair of second portions P2to each other.

An eighth conductive structure CP8 may be provided to be adjacent to theseventh conductive structure CP7. The eighth conductive structure CP8may extend from the PMOSFET region PR to the NMOSFET region NR. Theeighth conductive structure CP8 may be a pattern that is formed inaccordance with the eighth conductive pattern CL8 of FIG. 13. The eighthconductive structure CP8 may include a first portion P1 and a pair ofsecond portions P2.

The first portion P1 may be a pattern that is formed in accordance withthe eighth connection pattern M0 h of FIG. 13, and the second portionsP2 may be patterns that are respectively formed in accordance with theeleventh and twelfth active contact patterns CAk and CAl of FIG. 13.

For example, the second portions P2 may be connected to the lowerconductive structure TS on the PMOSFET region PR and the lowerconductive structure TS on the NMOSFET region NR, respectively. As anexample, the second portion P2 on the PMOSFET region PR may beoverlapped with the sixth interconnection line ML6, when viewed in aplan view.

The first portion P1 of the eighth conductive structure CP8 may includea pair of first extended portions HP1 extending in the second directionD2 and a second extended portion HP2 extending in the first directionD1. The pair of first extended portions HP1 may be overlapped with thepair of second portions P2, respectively. For example, the firstextended portion HP1 on the PMOSFET region PR may be provided to crossat least one of the gate electrodes GE. In other words, the firstportion P1 may connect the pair of second portions P2 to each other. Asa result, the source/drain regions SD on the PMOSFET region PR and thesource/drain regions SD on the NMOSFET region NR may be electricallyconnected to each other through the lower conductive structures TS andthe eighth conductive structure CP8.

In the case of the first conductive structures CP1 described above, thesource/drain regions SD on the PMOSFET region PR and the source/drainregions SD on the NMOSFET region NR may be connected to each other inthe first direction D1 through the second interconnection line ML2. Inthe case of the eighth conductive structure CP8, the source/drainregions SD on the PMOSFET region PR and the source/drain regions SD onthe NMOSFET region NR may be electrically connected to each other in thefirst direction D1 through the first portion P1 of the eighth conductivestructure CP8.

A seventh interconnection line ML7 may be provided on the eighthconductive structure CP8. The second extended portion HP2 of the eighthconductive structure CP8 may be partially overlapped with the seventhinterconnection line ML7, when viewed in a plan view. The seventhinterconnection line ML7 may be connected to the eighth conductivestructure CP8 through the second extended portion HP2.

FIGS. 18A and 18B are sectional views taken along line A-A′ of FIG. 16to illustrate a semiconductor device according to exemplary embodimentsof the present inventive concept. FIG. 18C is a sectional view takenalong line F-F′ of FIG. 16 to illustrate a semiconductor deviceaccording to exemplary embodiments of the present inventive concept. Inthe following description of the present embodiment, an elementpreviously described with reference to FIG. 16 and FIGS. 17A through 17Pmay not be described in much further detail for the sake of brevity.

Referring to FIGS. 16 and 18A, a first conductive structure CP1 may beprovided. Unlike the first conductive structure CP1 of FIG. 17A, thefirst conductive structure CP1 may further include a firstvertically-extended portion VP1. For example, a second portion P2 of thefirst conductive structure CP1 may include the first vertically-extendedportion VP1 vertically extending toward a substrate 100. The firstvertically-extended portion VP1 may be provided to cover an upperportion of a sidewall of a lower conductive structure TS. A bottomsurface of the first vertically-extended portion VP1 may be lower than atop surface of the lower conductive structure TS. When viewed in a planview, the first vertically-extended portion VP1 may be overlapped with afirst portion P1 of the first conductive structure CP1.

Referring to FIGS. 16 and 18B, a first conductive structure CP1 may beprovided. Unlike the first conductive structure CP1 of FIG. 17A, thefirst conductive structure CP1 may further include a pair of firstvertically-extended portions VP1. For example, a second portion P2 ofthe first conductive structure CP1 may include the pair of firstvertically-extended portions VP1 vertically extending toward a substrate100. The pair of first vertically-extended portions VP1 may be providedto cover upper portions of both sidewalls of the lower conductivestructure TS. Bottom surfaces of the first vertically-extended portionsVP1 may be lower than a top surface of the lower conductive structureTS. When viewed in a plan view, the first vertically-extended portionsVP1 may be overlapped with a first portion P1 of the first conductivestructure CP1.

Referring to FIGS. 16 and 18C, a second conductive structure CP2 may beprovided. Unlike the second conductive structure CP2 of FIG. 17F, thesecond conductive structure CP2 may further include a firstvertically-extended portion VP1 and a second vertically-extended portionVP2. For example, a second portion P2 of the second conductive structureCP2 may include the first vertically-extended portion VP1 verticallyextending toward a substrate 100, and a third portion P3 of the secondconductive structure CP2 may include the second vertically-extendedportion VP2 vertically extending toward the substrate 100. The firstvertically-extended portion VP1 may be provided to cover an upperportion of a sidewall of a lower conductive structure TS. A bottomsurface of the first vertically-extended portion VP1 may be lower than atop surface of the lower conductive structure TS. The secondvertically-extended portion VP2 may be provided to cover an upperportion of a sidewall of a gate electrode GE. A bottom surface of thesecond vertically-extended portion VP2 may be lower than a top surfaceof the gate electrode GE. When viewed in a plan view, the first andsecond vertically-extended portions VP1 and VP2 may be overlapped with afirst portion P1 of the second conductive structure CP2.

FIGS. 19, 21, 23, 25, 27, 29, and 31 are plan views illustrating amethod of fabricating a semiconductor device, according to exemplaryembodiments of the present inventive concept. FIGS. 20A, 22A, 24A, 26A,28A, 30A, and 32A are sectional views taken along lines A-A′ of FIGS.19, 21, 23, 25, 27, 29, and 31, respectively, FIGS. 20B, 22B, 24B, 26B,28B, 30B, and 32B are sectional views taken along lines B-B′ of FIGS.19, 21, 23, 25, 27, 29, and 31, respectively, FIGS. 22C, 24C, 26C, 28C,30C, and 32C are sectional views taken along lines C-C′ of FIGS. 21, 23,25, 27, 29, and 31, respectively, FIGS. 28D, 30D, and 32D are sectionalviews taken along lines D-D′ of FIGS. 27, 29, and 31, respectively, andFIGS. 30E and 32E are sectional views taken along lines E-E′ of FIGS. 29and 31, respectively. A method of fabricating a semiconductor deviceusing the standard cell layout of FIG. 13 will be described below. Forthe sake of simplicity, the description that follows will refer to anexample related to a fabrication method using the first standard cellSTDC1 of FIG. 16; however, this method may be applied for other standardcells (e.g., STDC2, STDC3, and so forth).

Referring to FIGS. 19, 20A, and 20B, a substrate 100 may be provided. Inexemplary embodiments of the present inventive concept, the substrate100 may be a silicon substrate, a germanium substrate, or asilicon-on-insulator (SOI) substrate. Active patterns FN may be formedin an upper portion of the substrate 100. First device isolationpatterns ST1 may be formed to fill a gap between the active patterns FN.The first device isolation patterns ST1 may be recessed to expose upperportions of the active patterns FN. Second device isolation patterns ST2may be formed on the substrate 100 to define a border between a PMOSFETregion PR and an NMOSFET region NR. In exemplary embodiments of thepresent inventive concept, when the second device isolation patterns ST2are formed, the active patterns FN may be removed from regions otherthan the PMOSFET and NMOSFET regions PR and NR. The active patterns FNon the PMOSFET region PR may be referred to as ‘first active patternsFN1’, and the active patterns FN on the NMOSFET region NR may bereferred to as ‘second active patterns FN2’.

The first and second device isolation patterns ST1 and ST2 may be formedby a shallow trench isolation (STI) process. The first and second deviceisolation patterns ST1 and ST2 may be formed of or include siliconoxide. The first device isolation patterns ST1 may be formed to have adepth less than that of the second device isolation patterns ST2. Inthis case, the first device isolation patterns ST1 and the second deviceisolation patterns ST2 may be formed by different processes. Inexemplary embodiments of the present inventive concept, the first deviceisolation patterns ST1 may be formed to have substantially the samedepth as that of the second device isolation patterns ST2. For example,the first device isolation patterns ST1 and the second device isolationpatterns ST2 may be formed at substantially the same time by the sameprocess.

Referring to FIGS. 21 and 22A to 22C, gate electrodes GE may be formedto cross the first and second active patterns FN1 and FN2 and to extendin a first direction D1. The gate electrodes GE may be spaced apart fromeach other in a second direction D2. A gate insulating pattern GI may beformed below each of the gate electrodes GE, and gate spacers GS may beformed on both side surfaces of each of the gate electrodes GE. Inaddition, a capping pattern CP may be formed to cover a top surface ofeach of the gate electrodes GE.

For example, the formation of the gate electrodes GE may include formingsacrificial patterns to cross the first and second active patterns FN1and FN2, forming gate spacers GS at both sides of the sacrificialpatterns, and replacing the sacrificial patterns with the gateelectrodes GE.

The gate electrodes GE may be formed of or include doped semiconductormaterials, conductive metal nitrides, or metals. The gate insulatingpattern GI may be formed of or include a silicon oxide layer, a siliconoxynitride layer, or high-k dielectric materials, whose dielectricconstants are lower than that of silicon oxide. Each of the cappingpattern CP and the gate spacers GS may be formed of or include a siliconoxide layer, a silicon nitride layer, or a silicon oxynitride layer.

Source/drain regions SD may be formed on or in the upper portions of thefirst and second active patterns FN1 and FN2. The source/drain regionsSD on the PMOSFET region PR may be doped with p-type impurities, whilethe source/drain regions SD on the NMOSFET region NR may be doped withn-type impurities.

In exemplary embodiments of the present inventive concept, thesource/drain regions SD may be epitaxial patterns, which are formedusing a selective epitaxial growth process. For example, the formationof the source/drain regions SD may include partially recessing the firstand second active patterns FN1 and FN2 at both sides of each of the gateelectrodes GE and performing the epitaxial growth process to form thesource/drain regions SD in the recessed regions of the first and secondactive patterns FN1 and FN2. The epitaxial growth process may beperformed using a semiconductor material different from that of thesubstrate 100. As an example, the source/drain regions SD may be formedof or include a semiconductor material having a lattice constantdifferent from (for example, greater or smaller than) the substrate 100.Since the source/drain regions SD are formed of a semiconductor materialdifferent from that of the substrate 100, the source/drain regions SDmay exert a compressive stress or a tensile stress on the channelregions AF therebetween.

Next, a first interlayer insulating layer 110 may be formed to cover thesource/drain regions SD and the gate electrodes GE. The first interlayerinsulating layer 110 may be formed of or include a silicon oxide layeror a silicon oxynitride layer.

Referring to FIGS. 23 and 24A to 24C, lower conductive structures TS maybe formed on the source/drain regions SD of the PMOSFET and NMOSFETregions PR and NR. Each of the lower conductive structures TS mayinclude at least a portion extending in the first direction D1 or mayhave a line- or bar-shaped structure. In addition, a portion of each ofthe lower conductive structures TS may be positioned on the seconddevice isolation pattern ST2, which is adjacent to the PMOSFET region PRor the NMOSFET region NR. The lower conductive structures TS may beformed to have top surfaces that are substantially coplanar with that ofthe first interlayer insulating layer 110.

For example, the formation of the lower conductive structures TS mayinclude patterning the first interlayer insulating layer 110 to formholes exposing the source/drain regions SD and filling the holes with aconductive material. Upper portions of the source/drain regions SD maybe etched or removed during the formation of the holes. The lowerconductive structures TS may be formed of or include doped semiconductormaterials, conductive metal nitrides, metals, or metal silicides.

Referring to FIGS. 25 and 26A to 26C, a second interlayer insulatinglayer 120 may be formed on the first interlayer insulating layer 110.The second interlayer insulating layer 120 may be formed of a siliconoxide layer or a silicon oxynitride layer.

A first photoresist pattern 125 may be formed on the second interlayerinsulating layer 120. The first photoresist pattern 125 may includeopenings, which are formed in accordance with the first connectionpatterns M0 a of FIG. 13. For example, the formation of the firstphotoresist pattern 125 may include forming a first photoresist layer onthe second interlayer insulating layer 120 and then performing anexposure and development process on the first photoresist layer using afirst photomask manufactured based on the first connection patterns M0 aof FIG. 13 (e.g., see steps S140 and S150 of FIG. 2).

The second interlayer insulating layer 120 may be patterned using thefirst photoresist pattern 125 as an etch mask to form connection holesM0 aH. The connection holes M0 aH may be formed to partially (e.g., notcompletely) penetrate the second interlayer insulating layer 120. Inother words, bottoms of the connection holes M0 aH may be higher thantop surfaces of the lower conductive structures TS and the gateelectrodes GE. Accordingly, the connection holes M0 aH may not exposethe top surfaces of the lower conductive structures TS and the gateelectrodes GE.

Referring to FIGS. 27 and 28A to 28D, the first photoresist pattern 125may be selectively removed. Thereafter, a first mask layer 140 may beformed on the second interlayer insulating layer 120. The first masklayer 140 may be formed to wholly fill the connection holes M0 aH.

A second photoresist pattern 145 may be formed on the first mask layer140. The second photoresist pattern 145 may include openings formed inaccordance with the first active contact patterns CAa and the secondactive contact patterns CAb of FIG. 13. For example, the formation ofthe second photoresist pattern 145 may include forming a secondphotoresist layer on the first mask layer 140 and then performing anexposure and development process on the second photoresist layer using asecond photomask manufactured based on the first and second activecontact patterns CAa and CAb of FIG. 13.

The first mask layer 140 and the second interlayer insulating layer 120may be sequentially patterned using the second photoresist pattern 145as an etch mask to form first active holes CAaH and second active holesCAbH. The first active holes CAaH may be hole patterns that arerespectively formed in accordance with the first active contact patternsCAa of FIG. 13, and the second active holes CAbH may be hole patternsthat are respectively formed in accordance with the second activecontact patterns CAb of FIG. 13.

The first and second active holes CAaH and CAbH may be formed tocompletely penetrate the second interlayered insulating layer 120. Inother words, the first and second active holes CAaH and CAbH may beformed to expose the top surfaces of the lower conductive structures TS.When viewed in a plan view, each of the second active holes CAbH may bepartially overlapped with a corresponding one of the connection holes M0aH. Each of the second active holes CAbH, in conjunction with each ofthe connection holes M0 aH, may be formed to constitute a singleconnection hole.

Referring back to FIG. 18A, if there is a misalignment in a process offorming the second active hole CAbH, a vertically-extended hole may beformed on a region that is overlapped with both of the second activehole CAbH and the connection hole M0 aH. In a subsequent step, thevertically-extended hole may be used to form a first vertically-extendedportion VP1, as shown in FIG. 18A. As a result of the process forforming the connection holes M0 aH, a portion of the second interlayerinsulating layer 120 may be thinner than other portions, and thus, thevertically-extended hole may be formed by the process for forming thesecond active hole CAbH.

As another example, if, as shown in FIG. 18B, the second active holeCAbH is formed to be wider than the lower conductive structure TS in thesecond direction D2, the vertically-extended hole may be formed on aregion that is overlapped with both of the second active hole CAbH andthe connection hole M0 aH. In a subsequent step, the vertically-extendedhole may be used to form a first vertically-extended portion VP1, asshown in FIG. 18B.

Referring to FIGS. 29 and 30A to 30E, the second photoresist pattern 145may be selectively removed. Next, a second mask layer 150 may be formedon the first mask layer 140. The second mask layer 150 may be formed tofill the whole regions of the first and second active holes CAaH andCAbH.

A third photoresist pattern 155 may be formed on the second mask layer150. The third photoresist pattern 155 may include an opening formed inaccordance with the first gate contact pattern CBa of FIG. 13. Forexample, the formation of the third photoresist pattern 155 may includeforming a third photoresist layer on the second mask layer 150 and thenperforming an exposure and development process on the third photoresistlayer using a third photomask manufactured based on the first gatecontact pattern CBa of FIG. 13.

A gate hole CBaH may be formed by sequentially patterning the secondmask layer 150, the first mask layer 140, and the second interlayerinsulating layer 120 using the third photoresist pattern 155 as an etchmask.

The gate hole CBaH may be formed to completely penetrate the secondinterlayer insulating layer 120. In addition, the gate hole CBaH may beformed to penetrate an upper portion of the first interlayer insulatinglayer 110. In other words, the gate hole CBaH may be formed to exposethe top surface of the gate electrode GE.

In exemplary embodiments of the present inventive concept, referringback to FIG. 18C, if there is a misalignment in a process of forming thegate hole CBaH or if the gate hole CBaH is formed to have an increasedwidth in the second direction D2, a vertically-extended hole may beformed on a region that is overlapped with both of the gate hole CBaHand the connection hole M0 aH. In a subsequent step, thevertically-extended hole may be used to form a secondvertically-extended portion VP2, as shown in FIG. 18C.

Referring to FIGS. 31 and 32A to 32E, the third photoresist pattern 155,the second mask layer 150, and the first mask layer 140 may be removed.Next, conductive structures AC, GC, and CP1 may be formed by filling theconnection holes M0 aH, the first and second active holes CAaH and CAbH,and the gate hole CBaH with a conductive material.

For example, active contacts AC may be formed in the first active holesCAaH. A gate contact GC may be formed in the gate hole CBaH. Firstconductive structures CP1 may be formed in the connection holes M0 aHand the second active holes CAbH, respectively. For example, the firstconductive structure CP1 may be formed by filling the connection hole,which is formed by the connection hole M0 aH and the second active holeCAbH, with the conductive material. In exemplary embodiments of thepresent inventive concept, the active contacts AC, the gate contact GC,and the first conductive structures CP1 may be formed at substantiallythe same time using the same process.

Barrier patterns BL may be respectively formed between the secondinterlayer insulating layer 120 and the active contacts AC, between thesecond interlayer insulating layer 120 and the gate contact GC, andbetween the second interlayer insulating layer 120 and the firstconductive structures CP1.

For example, the formation of the conductive structures AC, GC, and CP1and the barrier patterns BL may include conformally forming a barrierlayer to cover the connection holes M0 aH, the first and second activeholes CAaH and CAbH, and the gate hole CBaH, forming a conductive layerto completely fill the connection holes M0 aH, the first and secondactive holes CAaH and CAbH, and the gate hole CBaH, and performing aplanarization process on the conductive layer and the barrier layer toexpose the second interlayer insulating layer 120. The conductive layermay include conductive metal nitrides or metals, and the barrier layermay include metal nitrides capable of preventing diffusion of metallicelements.

Referring back to FIGS. 16 and 17A to 17E, a third interlayer insulatinglayer 130 may be formed on the second interlayer insulating layer 120.The third interlayer insulating layer 130 may be formed of or include asilicon oxide layer or a silicon oxynitride layer. First and secondpower interconnection lines PL1 and PL2 and first and secondinterconnection lines ML1 and ML2 may be formed in the third interlayerinsulating layer 130. The first and second power interconnection linesPL1 and PL2 and the first and second interconnection lines ML1 and ML2may be formed using a method that is similar to that for forming theconductive structures AC, GC, and CP1.

FIG. 33 is a plan view illustrating a semiconductor device that isfabricated based on standard cell layouts according to an exemplaryembodiment of the present inventive concept. In the present embodiment,the third standard cell layout STD3 of FIG. 13 is exemplarilyillustrated, but the present inventive concept may not be limitedthereto. In the following description of the present embodiment, anelement previously described with reference to FIG. 13 may not bedescribed in much further detail for the sake of brevity.

Referring to FIG. 33, the lower conductive patterns LP may not beincluded, unlike the previous embodiment of FIG. 13. Thirteenth toeighteenth active contact patterns CAm, CAn, CAo, CAp, CAq, and CAr maybe additionally disposed in place of the lower conductive patterns. Eachof the thirteenth to eighteenth active contact patterns CAm, CAn, CAo,CAp, CAq, and CAr may be overlapped with or connected to one of thePMOSFET region PR or the NMOSFET region NR.

The fifteenth active contact pattern Cao may be spaced apart from (e.g.,not overlapped with) the seventh connection pattern M0 g. Theseventeenth active contact pattern CAq may be spaced apart from (e.g.,not overlapped with) the sixth connection pattern M0 f. The eighteenthactive contact pattern CAr may be spaced apart from (e.g., notoverlapped with) the eighth connection pattern M0 h.

FIG. 34 is a plan view illustrating a semiconductor device according toexemplary embodiments of the present inventive concept. FIGS. 35Athrough 35C are sectional views taken along lines A-A′, B-B′, and C-C′,respectively, of FIG. 34. For example, FIG. 34 and FIGS. 35A through 35Cshow an example of a semiconductor device to be fabricated based on thestandard cell layouts of FIG. 33. In the following description of thepresent embodiment, an element previously described with reference toFIGS. 16 and 17A to 17R may not be described in much further detail forthe sake of brevity.

Referring to FIGS. 34 and 35A to 35C, the lower conductive structures TSmay not be included, unlike the previous embodiments of FIGS. 16 and 17Ato 17R. First to sixth active contacts AC1-AC6 may be additionallydisposed in place of the lower conductive structures. The first to sixthactive contacts AC1-AC6 may be structures that are defined by thethirteenth to eighteenth active contact patterns CAm, CAn, CAo, CAp,CAq, and CAr, respectively, of FIG. 33.

The source/drain regions SD adjacent to each other may be merged toconstitute a single body. Each of the first to sixth active contactsAC1-AC6 may be in contact with at least a portion of the mergedsource/drain regions SD. Since the merged source/drain regions SD areconnected to constitute the single body, it is unnecessary for each ofthe first to sixth active contacts AC1-AC6 to completely cover themerged source/drain regions SD. In addition, the second portion P2 ofeach of the fifth, seventh, and eighth conductive structures CP5, CP7,and CP8 may also be in contact with the merged source/drain regions SD,similar to the previous embodiments of FIG. 4.

As an example, referring to FIG. 35B, the third active contact AC3 maybe in contact with a portion of the merged source/drain regions SD.Accordingly, the first portion P1 of the seventh conductive structureCP7 may be disposed to cross the merged source/drain regions SD, withoutshort circuiting the third active contact AC3.

The first to sixth active contacts AC1-AC6 may have bottom surfaces,which are lower than those of the gate contacts GC and that of the thirdportion P3 of the sixth conductive structure CP6. Bottom surfaces of thesecond portions P2 of the fifth, seventh and eighth conductivestructures CP5, CP7, and CP8 may be lower than those of the gatecontacts GC and that of the third portion P3 of the sixth conductivestructure CP6.

According to exemplary embodiments of the present inventive concept, asemiconductor device may include a conductive structure that iselectrically connected to impurity regions or gate electrodes. Theconductive structure may include a horizontally extending portion, andthus, it is possible to freely dispose interconnection lines on theconductive structure. This makes it possible to realize a semiconductordevice with reliable operation characteristics.

While the present inventive concept has been particularly shown anddescribed with reference to exemplary embodiments thereof, it will beunderstood by one of ordinary skill in the art that variations in formand detail may be made thereto without departing from the spirit andscope of the present inventive concept as defined by the attachedclaims.

What is claimed is:
 1. A semiconductor device, comprising: a gateelectrode disposed on a substrate; a first contact disposed on the gateelectrode; a conductive structure disposed on the substrate and spacedapart from the gate electrode; a second contact disposed on theconductive structure; and a third contact directly disposed on the firstand second contacts and connecting the first and second contacts to eachother, wherein a first portion of the first contact is disposed in afirst insulating layer, and a top surface of the conductive structure iscoplanar with a top surface of the first insulating layer, wherein asecond portion of the first contact is disposed in a second insulatinglayer, and the second and third contacts are disposed in the secondinsulating layer, wherein a gap is formed between the second portion ofthe first contact and the second contact, the gap being filled with thesecond insulating layer, and the third contact extends across the gap toconnect with the second portion of the first contact and the secondcontact.
 2. The semiconductor device of claim 1, further comprising aconductor disposed on the substrate, wherein the conductive structure isdisposed between the gate electrode and the conductor.
 3. Thesemiconductor device of claim 1, further comprising: a via disposed onthe third contact; and a metal line disposed on the via.
 4. Thesemiconductor device of claim 3, wherein a bottom surface of the thirdcontact is coplanar with an upper surface of each of the first andsecond contacts.
 5. The semiconductor device of claim 1, wherein thegate electrode is a dummy gate electrode, the conductive structure isdisposed on a source or drain, and each of the first, second and thirdcontacts is conductive.
 6. The semiconductor device of claim 1, whereinthe first to third contacts are disposed between a first cell and asecond cell.
 7. The semiconductor device of claim 6, wherein the firstcell or the second cell is a static random access memory (SRAM) cell. 8.The semiconductor device of claim 1, wherein the first contact isdisposed on an upper surface and a side surface of the gate electrode.9. The semiconductor device of claim 1, wherein the second contact isdisposed on the top surface and a side surface of the conductivestructure.
 10. The semiconductor device of claim 1, wherein the topsurface of the conductive structure is disposed above an upper surfaceof the gate electrode.
 11. A semiconductor device, comprising: a gateelectrode disposed on a substrate; a first contact disposed on the gateelectrode; a conductive structure disposed on the substrate and spacedapart from the gate electrode, wherein the gate electrode, theconductive structure and a first portion of the first contact aredisposed in a first insulating layer; a second contact disposed on theconductive structure; a third contact directly disposed on the first andsecond contacts and connecting the first and second contacts to eachother, wherein the second contact, the third contact and a secondportion of the first contact are disposed in a second insulating layer;and a third insulating layer disposed on the second insulating layer,wherein a gap is formed between the second portion of the first contactand the second contact, the gap being filled with the second insulatinglayer.
 12. The semiconductor device of claim 11, wherein a bottomsurface of the second contact is disposed on an upper surface of theconductive structure.
 13. A semiconductor device, comprising: a gateelectrode disposed on a substrate, a longitudinal direction of the gateelectrode being parallel to a first direction; a first contact disposedon the gate electrode; a lower conductive structure disposed on thesubstrate and spaced apart from the gate electrode; a second contactdisposed on the lower conductive structure, the second contact beingspaced apart from the first contact in a second direction intersectingthe first direction in a first insulating layer; a third contactdirectly disposed on the first and second contacts and extending in thesecond direction, thereby connecting the first and second contacts toeach other, the first, second and third contacts constituting an upperconductive structure, and the first, second and third contacts aredisposed in the first insulating layer; and a barrier pattern covering abottom surface and side surfaces of the upper conductive structure,except a top surface of the upper conductive structure, wherein a widthof the third contact in the first direction is greater than a width ofthe first contact in the first direction.
 14. The semiconductor deviceof claim 13, further comprising a conductor disposed on the substrate,wherein the conductive structure is disposed between the gate electrodeand the conductor.
 15. The semiconductor device of claim 13, furthercomprising: a via disposed on the third contact; and a metal linedisposed on the via.